(1) Field of the Invention
The present invention relates to a process used to fabricate semiconductor devices, and more specifically to a process used to create insulator spacers, on the sides of a gate structure.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still maintaining, or decreasing the manufacturing costs for these same semiconductor devices. The arrival of micro-miniaturization, or the ability to fabricate semiconductor devices using sub-micron features, have contributed to the attainment of the performance and cost objectives. Semiconductor devices comprised with sub-micron features result in a decrease in performance degrading capacitances and resistances. In addition the use of sub-micron features allows smaller semiconductor chips, still containing device densities achieved with larger counterparts, to be realized, thus resulting in a greater number of semiconductor chips to be obtained from a specific size starting substrate, thus reducing the processing cost for a specific semiconductor chip. Specific semiconductor fabrication disciplines such as photolithography and dry etching, have been major contributors of the trend to micro-miniaturization. For example the use of more sophisticated exposure cameras, as well as the use of more sensitive photosensitive materials, have allowed sub-micron images to be routinely formed in photoresist layers. In addition the development of more advanced dry etching tools and processes, have allowed the sub-micron images, in photoresist layers, to be successfully transferred to underlying materials, used in construction of semiconductor devices.
However, in addition the contributions made via use of advanced semiconductor fabrication disciplines, specific structural contributions, such as the use of a self-aligned contact, (SAC), structure, has also enabled smaller, faster, semiconductor devices to be successfully realized. The SAC concept entails opening a contact hole, to expose a source/drain region, located between gate structures. In order to maintain a minimum space between gate structures, and to have a SAC structure fully land on the source/drain region, the diameter of the contact hole, used to expose the source/drain, would have to be smaller then current photolithographic technology can now supply. Therefore the SAC concept is used, opening a hole larger in width than the space between gate structures, exposing the source/drain region, however also exposing a top portion of the neighboring gate structures. The gate structures are comprised of a top layer of silicon nitride, as well as silicon nitride spacers, on the sides of the gate structure. Therefore a subsequent, conductive SAC structure, is formed, larger in width than the diameter of the SAC opening, thus contacting the source/drain region, in the SAC opening, however interfacing only regions of silicon nitride, in areas in which the conductive SAC structure, overlaps the SAC opening.
The SAC opening is formed in an insulator layer, usually a boro-phosphosilicate, (BPSG), layer. The BPSG layer is deposited, after insulator spacer formation, directly overlying exposed source/drain regions. With this scenario, dopants such as boron and phosphorous, residing in the BPSG layer, can interface and diffuse into exposed source/drain region, resulting in unwanted compensation of the these regions. In addition the SAC opening, performed using an anisotropic RIE procedure, can result in removal of silicon oxide isolation regions, at end point, or during an overetch cycle. This invention will describe a procedure for forming SAC openings, without the vulnerability of doping exposed source/drain regions, or without damage to silicon oxide isolation regions. This invention features a partial formation of silicon nitride spacers, leaving a thin layer of silicon nitride on the source/drain regions, between gate structures. The thin silicon nitride layer protects the source/drain region from BPSG out diffusion. This invention also features a two step SAC opening procedure, comprised of a first step in which the RIE chemistry removes BPSG at a much greater rate than silicon nitride, thus stopping at the thin silicon nitride layer, followed by a second RIE procedure, used to remove the thin silicon nitride layer, using a RIE chemistry that results in faster removal rates of silicon nitride, compared to silicon oxide. Prior art, such as Chien, et al, in U.S. Pat. No. 5,643,824, describe a process for using silicon nitride extensions, to prevent "birds beak" formation during the growth of field oxide regions. In addition Barber et al, in U.S. Pat No. 4,966,870, describe a process for fabricating a borderless contact. However these prior arts do not use a thin silicon nitride layer, overlying source/drain regions, nor does it use a two step, anisotropic RIE procedure to selectively form a SAC opening, and then to selectively remove the thin silicon nitride layer.